Tuesday, May 8, 2012
Very exciting, fast growing, 5 year old start- up company currently in stealth mode, developing interesting SoCs & platforms in a close collaboration with various partners and customers. Company has just closed a large round of financing and has solid financial backing from large corporate and financial investors. Founded by an experienced team with many industry notables involved in various capacities. Company currently employs approximately around 250 people worldwide.
Staff ASIC/SoC Verification Engineer
Will be one of the leading members of a large Design Verification team. Responsible for pre-silicon RTL design verification of a complex low power high performance CPU core and ASIC SoC that includes digital and analog cores. Some of the responsibilities include but not limited to testbench/testplans development block level verification, full-chip verification, coverage driven verification, system & architectural compatibility verification and assertions driven verification. You will also be responsible for mentoring and training Junior Engineers.
* 7-10 years of industrial experience in pre-silicon verification
* Experience with setting up the Verification environment for a large complex SoC
* Hands on experience with SystemVerilog, NTB/VERA, SPECMAN, C/C++ and Perl
* Must be familiar with OVM, VMM, ERM concpets
* Processor verification background is desired
* Must be familiar with one or more of, SPARC, X86, MIPS, ARM and PowerPC.
* Must have verified complex SoC ASICs.
Developing testbenches for CPU logic blocks, processor cores, coprocessor cores, and other digital logic devices in SystemVerilog, C and C++.
Writing test plans for the above mentioned DUT-s (Design Under Test).
Writing and debugging tests for the above mentioned DUT-s using SystemVerilog, Perl, Assembly, C, C++ and possibly other languages. Writing Random Test Generators to automatically and intelligently generate the bulk of tests. Writing coverage monitors to evaluate the coverage of the DUT-s.
Writing system level tests for next generation chips.
Participating in chip bringup.
The successful candidate possesses a master’s degree in EE or CS.
Versatile and skilled both in Verilog SystemVerilog as well as C/C++/Perl and Assembly.
Strong communication skills and a strong team player.